1. Field of the Invention
This invention relates to a simulation method of a silicide reaction for use with production of semiconductor device, and more particularly to a simulation method for setting conditions when a silicide film of a metal having a high melting point is formed on a diffused layer in source/drain regions and so forth or on gate electrodes of MOS transistors.
2. Description of the Related Art
Refinement and Increase in density of semiconductor devices or integrated circuit devices have been and are being proceeded energetically, and at present, semiconductor devices of a very high integration degree such as memories and logic elements designed with a dimensional reference of 0.15 to 0.25 microns are produced.
As the degree of integration of semiconductor devices increases in this manner, it becomes important to reduce the dimensions in width of a diffused layer in source/drain regions and so forth and in width of gate electrodes and reduce the film thickness of a material which forms semiconductor devices.
On the other hand, reduction of the width of gate electrodes or of gate electrode wirings and the thickness of the gate electrode material inevitably gives rise to increase the wiring resistances of them and thus has a significant influence on the delay of the circuit operation. Therefore, for refined semiconductor devices, a technique for reduction in resistance of the gate electrodes for which high melting point metal silicide is used cannot be avoided. Particularly, a self-align-silicide (salicide) technique which uses titanium as a high melting point metal is an important technique for fine MOS transistors.
Here, a conventional method of manufacturing a MOS transistor having a salicide structure is described with reference to FIGS. 6(a) to (e).
First, an element separating insulation film 602 is formed in a region of a surface of a silicon substrate 601, on which no MOS transistor is to be formed later, as shown in FIG. 6(a) using a known LOCOS technique. Then, ion implantation of an impurity for a channel stopper is performed with the same conduction type as that of the silicon substrate 601 on the surface of the silicon substrate 601 under the element separating insulation film 602. Thereafter, the exposed surface of the silicon is thermally oxidized to form a gate insulation film over the entire area.
Then, a polycrystalline silicon film of approximately 150 nm thick is formed over the entire area by a chemical vapor phase deposition method (CVD), and an impurity such as phosphor is doped. Thereafter, the polycrystalline silicon film and the gate insulation film are selectively removed using a lithography technique and a dry etching method to form a gate insulation film 603 and a gate electrode 604 of a desired shape. Thereafter, a silicon oxide film is deposited over the entire area using a chemical vapor phase deposition method (CVD), and a spacer 605 of the silicon oxide film is left only on side faces of the gate insulation film 603 and the gate electrode 604 by anisotropic dry etching.
After a gate electrode structure is produced in this manner, diffusion of an impurity of arsenic or boron is performed by heat treatment at 800.degree. C. to 1,000.degree. C. to form a diffused layer 606 for a source region, a drain region and so forth. Here, where the MOS transistor to be produced is of the N-channel type, arsenic is selected as the impurity, but where the MOS transistor is of the P-type, boron is selected as the impurity.
Then, a titanium film 607 of approximately 50 nm thick is formed over the entire area by a metal sputtering method or the like as shown in FIG. 6(b). Then, heat treatment is performed for 30 to 60 seconds in a nitrogen atmosphere of an atmospheric pressure. This heat temperature is normally performed by a lamp annealing apparatus, and the heat treatment temperature is set to 600.degree. C. to 650.degree. C. Silicification of the titanium is performed in this manner. As a result of such heat treatment, such a structure as shown in FIG. 6(c) is obtained. Referring to FIG. 6(c), on the surface of the gate electrode 604 of the polycrystalline silicon film and the diffused layer 606 in the source/drain region and so forth, a silicide layer 609 of a C49 structure which is a crystal structure, having a high electrical resistivity, is formed in a contacting relationship with them, and a titanium nitride layer 608 is formed on the silicide layer 609. In contrast, the titanium nitride layer 608 is formed in a contacting relationship on the element separating insulation film 602 in the form of a silicon oxide film and the spacer 605 over the entire area.
Then, the titanium nitride layer 608 is removed as shown in FIG. 6(d) using an ammonia solution and a solution obtained by mixing pure water into a hydrogen peroxide solution. As a result of this step, the silicide layer 609 of the C49 structure is left in a self-aligned relationship only on the gate electrode 604 and the diffused layer 606 in the source/drain region and so forth.
Further, second heat treatment is performed for approximately 60 seconds in a nitrogen atmosphere of an atmospheric pressure. Also this heat treatment is performed by lamp annealing, and the processing temperature is set to approximately 850.degree. C. As a result of this heat treatment, the silicide layer 609 of the C49 structure changes to a silicide layer 610 of the C54 structure which is a crystal structure having a low electrical resistivity as shown in FIG. 6(e). A wiring layer of aluminum or some other metal is formed on the silicide layer 610 of the C54 structure to form an electric circuit.
However, as the refinement and the increase in density of devices increase, refinement of the gate electrode 604, the diffused layer 606 in the source/drain region and so forth in each of MOS insulated gate field effect transistors formed in this manner proceeds so that the widths of them are very narrow. As reduction in width proceeds in this manner, it becomes difficult to form a silicide layer of a low electrical resistivity on them. In particular, if the contacting region is small, then a sufficient amount of silicon cannot be supplied and the procedure of a silicification reaction is suppressed, and consequently, sufficient silicide is not formed. Even if sufficient silicide is formed, the electrical resistivity cannot still be reduced sufficiently.
Therefore, prior to high density formation of fine MOS insulated gate field effect transistors, it must be confirmed in the stage of designing whether or not a region (particularly in terms of the width) in which a silicide film having a sufficient electrical resistivity can be formed has been assured. In such confirmation, optimum conditions must be found out taking not only the widths of the gate electrode 604, the diffused layer 606 in the source/drain region and so forth but also various conditions in the silicide formation steps such as the film thickness of the high melting point metal such as titanium and the heat treatment temperature, heat treatment time and so forth in the heat treatment, the impurity surface concentrations of the gate electrode 604 and the diffused layer 606 and so forth into consideration. Those optimum conditions can be determined readily if a two-dimensional process simulation technique in which a silicide formation process which can be applied to a process of producing fine MOS field effect transistors is established.
Several proposals have been made for such a two-dimensional process simulation technique as described above. One of the techniques is disclosed in a report by C. M. Li, T. Crandle, M. Temkin and P. Hopper, "A Two-Dimensional Process Model for Silicide Growth", International Workshop on VLSI Process and Device Modeling, 1993, pp. 68-69. In this technique, a silicide formation process is analyzed using a diffusion efficiency.
Subsequently, this technique is described with reference to FIG. 5. First, for a heat treatment step for formation of silicide, a heat treatment temperature and a heat treatment time are set (step 301).
Then, diffusion equations for silicon and metal atoms in silicide are solved (step 302). According to the prior art technique, diffusion of silicon and metal atoms in silicide is described using a point defect diffusion process. A time function of the concentration C.sub.i of silicon or metal atoms can be obtained by solving the following diffusion equation (1): ##EQU1## where D is the diffusion coefficient, and R the recombination frequency of silicon and metal. From a solution of the equation, a concentration of the silicide at each position is obtained.
Thereafter, a diffusion rate at the interface between silicon and silicide (step 303) and a diffusion rate at the interface between metal and silicide (step 304) are calculated. The diffusion rates at the interfaces (that is, the growth rates) are calculated by the same calculation, and the diffusion rate (growth rate) at the ith point of each of the interfaces is calculated in accordance with the following expression (2): ##EQU2## where k.sub.i is the reaction rate coefficient at the interface, N.sub.i the number of metal or silicon atoms consumed per unit silicide amount, C.sub.i the concentration of metal or silicon atoms on the silicide side of the interface, and n.sub.i a vector normal to the interface.
Subsequently, it must be taken into consideration whether the two interfaces including the interface between metal and silicide and the interface between silicide and silicon are same as or different from each other. In order to solve the diffusion equation in this instance, the following procedure must be followed. First, from the growth rate of the silicide, the moving speeds of the interface between silicon and silicide and the interface between metal and silicide are calculated, and the interfaces are moved in accordance with the moving speeds for a very short period of time (step 305). In this stage, visco-elasticity calculation is performed and the profiles of the interfaces are deformed. Then, using the results as boundary conditions, an impurity distribution of the bulk (silicon) is calculated by solving the diffusion equation (step 306).
By the foregoing steps, a state at a certain point of time is made clear. The proceeding situation of the diffusion can be obtained by repetitively performing the calculation after the time is advanced (step 307).
According to the solving method which uses the phenomenalistic diffusion equation of C. M. Li et al. described above, the diffusion equation for an impurity concentration is solved using the interface between metal and silicide and the interface between silicide and silicon as boundary conditions, and then, those interfaces are moved in accordance with the growth rate of silicide calculated separately from the impurity distribution. In this solution, the mutual dependency of the silicide formation and the impurity distribution is taken into consideration but merely in a phenomenalistic sense in the form of an impurity flux and a deformation flux in the interface caused by the movement of the interface. Therefore, the prior art solving method described above fails to represent a phenomenon that, where the width is small, a silicide reaction is suppressed from the fact that plastic deformation of a high melting point metal film described below is not taken into consideration.
In particular, the prior art solving method does not take the phenomenon into consideration that a silicide film itself sinks into silicon as a silicide reaction proceeds. This phenomenon arises from silicon diffusion originating from the silicide reaction. Particularly in a silicon region surrounded by an insulating substance, if sinking of the silicide film proceeds, then plastic deformation of the high melting point metal film occurs as the silicide is deformed. In this instance, where the silicon region has a small width, since the length of the span over which the silicide is supported on the insulation film is short, the force necessary for plastic deformation of the high melting point metal increases. As a result of the increase of the material strength of the high melting point metal film, diffusion of the high melting point metal film is suppressed, and consequently, the rate of the silicide reaction drops. In this manner, where the silicon region is a region having a small width, particularly the reduction of the rate of the silicide reaction matters, and even if a metal wiring of aluminum or a like metal is formed on the silicide region, sufficient connection cannot be established with a low resistance.
In this manner, the prior art solving method which uses the phenomenalistic diffusion equation has a problem in that a silicide reaction from a point of view of the strength of materials of a high melting point metal is not taken into consideration. Consequently, the phenomenon that a drop of the reaction rate of silicification occurs with a wiring of a small width originating from the film strength of the high melting point metal film is not represented, and as a result, the prior art solving method is disadvantageous in that simulation of the phenomenon that silicide of a low resistivity cannot be formed in a narrow wire region cannot be achieved. In other words, the simulation fails to obtain a pointer to a limitation in refinement which is most important in development of semiconductor devices. Consequently, the prior art solving method exhibits a contradiction that, although silicide is formed according to the prior art solving method which uses the phenomenalistic diffusion equation, in actual manufacture of semiconductor devices, sufficient silicification is not achieved.